Double data rate (DDR) transmission uses both the falling edge and the rising edge of a data clock for data transmission and reception. A DDR source transmits a data bit or word at every clock edge. Similarly, a DDR receiver receives a data bit or word at every clock edge. In contrast, single data rate transmission at the same clock rate would be twice as slow since only one of the clock edges would be used. Although the use of DDR is thus quite popular, it faces a number of challenges due to its more stringent timing requirements as compared to single edge data transmission.
For example, the DDR clock should have a 50% duty cycle. One can readily appreciate why in that a 50-50 split of the duty cycle for the rising/falling edges of the clock allows the receiver and transmitter the most time possible with each clock edge. As the duty cycle strays from this ideal 50-50 split, one of the clock states has less of each clock cycle than the remaining state. The data eye for the receiver then begins to collapse for the shortened clock state, which leads to undesirable data transmission errors.
Given the importance of striving for a 50% duty cycle, various duty cycle correcting circuits have been implemented. In that regard, a DDR source transmits both the clock and the corresponding data to the DDR receiver. So the data path and the clock path should have balanced delays. Since the duty cycle correction circuit is inserted into the clock path, the duty cycle correction circuit should have a small as possible insertion delay so as to not increase jitter. But conventional duty cycle correction circuits often have undesirable levels of insertion delay. For example, one duty cycle correction technique involves selectively increasing the switching currents in PMOS and NMOS devices for the rising and falling clock edges. This technique has a limited range of correction so to achieve a wide correction range requires several stages cascaded together, which leads to a large insertion delay and also demands more power.
An alternative conventional duty cycle correction circuit involves the use of one of the current clock edges (either rising or falling) to generate a half-cycle clock pulse. To produce the remaining complementary clock edge to complete a clock cycle, the duty cycle correction circuit delays the current clock edge by a half clock cycle and inverts it to create the complementary edge. Although this technique provides a greater range of correction compared to varying the switching currents, note that the clock frequency for a DDR system may range from a relatively low frequency such as a few hundred MHz to several GHz. At the lower frequencies, the half clock cycle delay necessary to generate the complementary clock edge becomes appreciable. Implementing such a lengthy delay demands substantial amounts of power.
Accordingly, there is a need in the art for improved duty cycle correction circuits that are power efficient with minimal jitter and distortion.